CIRCUIT WORKS / ENGINEERING NOTEBOOK
Four original RTL studies, from processor pipelines to the fabric that moves their data. Specifications, testbenches, reference models, and measured results are published together.
Four five-stage integer pipelines sharing a memory port, with forwarding, hazard control, precise terminal traps, and architectural trace verification.
make cpuAn output-stationary MAC array with skewed operand delivery, tail masking, backpressured results, and measured fill-and-drain utilization.
make systolicTagged sector coalescing and a banked scratchpad that expose the cost of strided accesses, broadcasts, conflicts, and out-of-order memory replies.
make memoryBuffered mesh routers with deterministic routing, fair output arbitration, stable grants under backpressure, and packet-level contention experiments.
make nocThe tests compare architectural behavior and complete transactions. The documentation separates implemented features, measured behavior, design reasoning, and future work.
Independent educational implementations developed with AI assistance. No production GPU, fabricated silicon, physical timing, or compliance certification is claimed.