RTL / ARCHITECTURE / VERIFICATION
Inside the
compute fabric.
Computer architecture studies with RTL you can inspect, tests you can run, and results you can reproduce.
RTL architecture projects
Compute / Memory / InterconnectFour-Core RV32I Cluster
Four five-stage integer pipelines sharing a memory port, with forwarding, hazard control, precise terminal traps, and architectural trace verification.
25,668 retirement events checked
INT8 Systolic Accelerator
An output-stationary MAC array with skewed operand delivery, tail masking, backpressured results, and measured fill-and-drain utilization.
1,344 matrix elements checked
GPU-Style Warp Memory
Tagged sector coalescing and a banked scratchpad that expose the cost of strided accesses, broadcasts, conflicts, and out-of-order memory replies.
18,096 lane values checked
Mesh Network-on-Chip
Buffered mesh routers with deterministic routing, fair output arbitration, stable grants under backpressure, and packet-level contention experiments.
33,120 packets checked
Open the engineering notebook.
Architecture guides, interface contracts, verification matrices, measured results, and design-review walkthroughs.
Applied systems & research
Semiconductor controls, forecasting, and energy research.
AMHS FOUP Digital Twin
A semiconductor-fab digital twin connecting transport scheduling, servo motion, safety interlocks, and a live browser control room.
06PRISCA SPY Predictor
A collaborative forecasting pipeline combining historical market data and financial-news sentiment to predict the next SPY opening price.
07Solar Power Forecasting
Machine learning research that turns historical weather and energy data into solar-generation forecasts.