The idea
The layout of a warp’s addresses can matter as much as its arithmetic. This project studies two complementary structures: a global-load coalescer and shared-memory banks with conflict replay.
The approach
The coalescer groups active word addresses into 32-byte sectors, issues uniquely tagged requests, and gathers reordered replies into lane order. The scratchpad chooses one distinct word per bank per clock, broadcasts matching loads, and replays unresolved conflicts.
Engineering work
- Implemented lane masks, sector grouping, concurrent outstanding requests, response-tag tracking, and complete-warp assembly.
- Built explicit storage banks with one write port per bank and deterministic same-word store behavior.
- Checked contiguous, offset, strided, broadcast, empty, invalid, and random access patterns at 8 and 32 lanes.
- Verified every lane value, sector count, and bank-service count against independent models under randomized timing.
What the results show
Thirty-two contiguous aligned words require four sector requests; shifting the first address by one word requires five. A stride of eight words requires 32. The verification run observed 17 sector requests in flight and exercised reply reordering.
Verification evidence
| Warp operations | 948 |
|---|---|
| Lane values compared | 18,096 |
| Observed requests in flight | 17 |
| Tested scratchpad banks | 4 / 8 / 16 |
Each project includes a documented test plan and coverage gaps. Simulation checks the supplied workloads; generic cell counts are not physical area, timing, or power measurements.
Reproduce the result
Download the source, install the open-source tools, and run from the collection root:
make memory
make lint
make synth
make report